Compiler directive & System tasks in Verilog | #14 | Verilog in English

preview_player
Показать описание

#vlsipoint #verilog #VLSI #HDL #verilog_in_english
#System_tasks
#Compiler_directives
#Internal_variable_monitoring_system_task
#Simulation_control_tasks
#Simulation_time_related_tasks

System tasks (ST)
1. Internal variable monitoring ST
2. Simulation control Tasks
3. Simulation time related Tasks

There are tasks and functions that are used to generate input and output during simulation. Their names begin with a dollar sign ($).

1. Internal variable monitoring ST

$display
$write
$strobe
$monitor
$random

2. Simulation control Tasks

$reset
$stop
$finish

3. Simulation time related Tasks

$time
$stime
$realtime

Compiler directives

A compiler directive may be used to control the compilation of a Verilog description. The grave accent mark( ` )denotes a compiler directive.
A directive is effective from the point at which it is declared to the point at which another directive overrides it, even across file boundaries.

`define
`include
`timescale

Don't miss the Verilog videos:

Introduction to HDL | What is HDL? | #1 | Verilog in English

Level of abstraction in Verilog | #2 | Verilog in English

Modules and Instantiation in Verilog | #3 | Verilog in English

Simulation, Synthesis and Design methodology in Verilog | #4 | Verilog in English

Data types in Verilog | #5 | Introduction | Verilog in Hindi | VLSI Point

Net Data type in Verilog | #6 | Verilog in English | VLSI Point

Reg Datatype in Verilog | # 7 | Verilog in English | VLSI Point

Vectors, Arrays, Memories, Parameters, Strings in Verilog | #8 | verilog in English | VLSI Point

Operators in Verilog | #9 | Verilog in English | VLSI Point

Practice-Set | #10 | Verilog in English | VLSI Point

Gate Level Modeling | #11 | Verilog in English | VLSI Point

Dataflow Modeling | #12 | Verilog in English | VLSI Point

Behavioral Modeling | #13 | Verilog in English | VLSI Point

Compiler directive & System tasks in Verilog | #14 | Verilog in English

Reference- verilog HDL : A Guide to Digital Design and Synthesis
By Samir palnitkar
Рекомендации по теме
Комментарии
Автор

at 1:24 in 2nd point i think instead of $strobe there should be $write. correct me if i am wrong

riyazuddinmohammed
Автор

superb good work. kindly please make video course on UVM too

nasirkhan-zkdm
Автор

i am not getting same output as you. $monitor is not working the way you demonstrated it here. 3:56

sentient
Автор

Mam if we have two blocking statement like
a=0;
a=1;
$display("a = ", a);
$monitor("a= ", a);
what will be the output mam?

bhuwankaushik
Автор

Hello Ma'am!!
Please can you make a series on VHDL Language too!!

kingwon
Автор

Hello
The telegram group link doesn’t work do can you send another one?

ramazain
Автор

The given telegram link has expired can u provide new link to ask some doubts in verilog

shaiksaleem
Автор

It was too fast. Could not understand clearly...

ganeshbagnal
Автор

Hi Didi...
can u just go a bit slow in videos???
Becaus it is quite difficult to catch your words and points which u r saying

darsanraj