Computer Architecture - Lecture 26: On-Chip Networks (Fall 2023)

Lecture 26: On-Chip Networks
Date: January 26, 2024

Recommended Reading:
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A Modern Primer on Processing in Memory

Intelligent Architectures for Intelligent Computing Systems

RowHammer: A Retrospective

Fundamentally Understanding and Solving RowHammer

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Computer Architecture Fall 2021 Lectures Playlist:

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The Story of RowHammer Lecture:

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Computer Architecture Fall 2020 Lectures Playlist:

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Rethinking Memory System Design Lecture @stanfordonline :

[Edwinthebreadwin]

Thank you for making this amazing series public

[pyzcgxl]

How can one prototype this (packet scheduling, etc) on fpgas? As switches in fpgas don't have transistors for logic like in the clbs, instead only has minimal (pass/ access transistor), which are configured on device boot-up based on the bit-stream.

Also, can any of these prototypes by any chance be writen using high level synthesis (hls), or hdl is necessary?