verilog code for comparator | user definied primitives in verilog

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comparator design in verilog user defined primitives
In this video, design of comprator as user defined primitive is explained.

let us discuss if anything wrong. comment your answers.

0:00 question and description
2:00 comparator module definition

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Yes Sir, I was also Able to make this Verilog Module using the user defined primitive concept

criss_royy

This video was very helpful. Got the required output thank u sir

renusiddagangappa

Hi sir, can we use if ({A1, A2, A3}> {B1, B2, B3}) then C=1

mdhafsa

I have been following you since long.

But why you have not uploaded any further assignment answers after this.

I have to answer the week 5 programming assignment 2. But unable to get the idea. also that is not uploaded by you

Today is last date

Please upload it ASAP

GAURAVSHARMA-evlb

Sorry for the trouble but when i compile the test cases all correct sir, when i click submit it says wrong ans. I checked every line of code, its correct but dono y its showing wrong ans after submitting. I have taken screen shot but unable to attach here. kindly help

renusiddagangappa

When we compile all test cases passed but when we submit it says test cases are wrong. should we write tb also?

renusiddagangappa

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