Optimizing RISCV FPGA by caching spi flash in sram and a new open source soft core!

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0:00 Introduction
5:00 New PicoRV RISCV core!
20:00 Running ROM code from SRAM cache
  1. Bits inside by René Rebe
  2. code
  3. gcc
  4. risc
  5. cisc
  6. picorv
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