DesignWare 112G Ethernet PHY IP JTOL & ITOL Performance | Synopsys

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This video shows the Synopsys 112G Ethernet PHY IP in TSMC’s N7 process passing the jitter and interference tolerance test at the IEEE-specified bit error rate (BER). The IP with leading power, performance, and area is available in a range of FinFET processes for high-performance computing SoCs.  

  1. Synopsys
  2. designware ip
  3. 112G Ethernet phy ip
  4. high-speed serdes phy ip
  5. jtol
  6. itol
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Minute 1:28, when talking about the channel the caption says: "As the ISI channel used for this test has a 3dB loss at 26GHz...". Should instead be 30dB == 10in stripline trace?

sneally