Neural Networks on FPGA: Part 10: Automatic Generation of Neural Networks for FPGAs

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zynet git repo
Tutorial Source code
  1. Vipin Kizheppatt
  2. neural network
  3. fpga
  4. zynq
  5. Xilinx
  6. Verilog
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Комментарии
Автор

Hello. Thanks for your informative videos. I am facing one issue in the simulation, each time i run, the accuracy is text is not being displayed in the Tcl console, am using Vivado 2021.1 version(if that helps)

sourabh
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Hello, when I was running the code in the video, nothing else was wrong. I could have generated the SRC folder, but Zynet. makeXilinxProject('myProject1', 'xC7z020clG484-1 ') failed, indicating that Vivado was not an internal or external command, nor a program that could be run.
I used Vivado 2018.3, which can be used normally. I have added the path of Vivado(E:\vivado2018.3) to the environment variable. What is the cause of compilation failure? And how to deal with this problem?

marcuszhang
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Nice work Sir, where is the input data set to the input layer?

muhammedfayas
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Thank you for your tutorials!
However, I meet a problem---- when I run mnistZyNet.py, it shows that "The RDI_DATADIR environment variable is not set".(I have installed python 37 and pip numpy&zynet, and also added corresponding directories of Vivado to the Path)
I will be grateful if I can get your reply!

早木由
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Really helpful, thanks for the tutorial

zhenyazang
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Hello, I have a little question about your code.
You don't declare input_layer in the network structure, and they're also no input_layer liker tensorflow in zynet, so the Output Shape of model.summary() is multiple. Did it make a difference in the final training?

marcuszhang
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I want a project like this, How can I contact you

swagswamy
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Hi sir, thanks for the great tutorial.I have some problem I want to simulate this code with modelsim through vivado.i add libraries that needed, but when i run simulation in tcl console shows this error:
Error: failed.
# Error in macro ./top_sim_compile.do line 29
# failed.
would you mind help me to solve it??

anahitahosseinkhani
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Hello, I watched all the series and it is really great thank you. I have a question though, what modifications you think can be done here to have the same flow you worked with in order to implement a CNN? You think it is possible to implement a CNN using the same method but with few teaks? Thanks a lot you have been a great help!

XxFarnawanyxX
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Wow, great idea about automating design!! Previously, I thought about making blocks manually in verilog, but with this, I think I can try different designs easily!!! Thanks Vipin for great video.

By the way, other than zynet, in previous video you mentioned about adding CNN. Have you also tried CNN? Also, do you plan to make video on camera-fpga-Zynet design?

SangHyun-rxrx
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Hello, may I ask whether the version of IP core generated by Zynet is determined according to the version of Vivado on my computer or only the version of Vivado 2017 can be generated? Can the IP core suited to Zynq ultrascale MPsoc and Vivado2019 be generated?

marcuszhang