CXL™ (Compute Express Link™): Advancing coherent connectivity

Presented by Mahesh Wagh (CXL Consortium (AMD)

Delivering high-performance interoperable computational infrastructures is vital to meet the exponential growth of global data. CXL™ (Compute Express Link™), an open interconnect standard, delivers coherency and memory semantics using high-bandwidth, low-latency connectivity between the host processor and accelerators, memory buffers, and smart I/O devices to deliver optimized performance in evolving usage models.

CXL 3.0 expanded on previous specification iterations to increase scalability and optimize system-level flows with advanced switching and fabric capabilities, efficient peer-to-peer communications, and fine-grained resource sharing across multiple compute domains. In addition to memory pooling, CXL 3.0 introduced memory sharing, allowing system architects to deliver advancements to existing systems. CXL 3.0 also includes fabric capabilities beyond the traditional tree-based architectural structures of PCI Express® (PCIe®) and previous CXL iterations.