SLL Logical Shift Left 8 bit RTL Code in Verilog and VHDL with Testbench. Using Behavioral Modeling.

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#SLL #Logical #Shift #Left #Design #RTL #Code 8 bit in #Verilog and #VHDL with #Testbench. Using #Behavioral #modeling

SV SLL RTL code:

// behavioral model for shift left (its not a shift register)
module shift_left_logic_8(s, a, b);

output [7:0] s;
input [7:0] a, b;
wire [7:0] s1, s2;

//assign s = a ＜＜ b[2:0]; //this is shift left

// assign s = (b[2:0] == 0) ? a:// 000
// (b[2:0] == 1) ? {a[6:0],1'b0}://001
// (b[2:0] == 2) ? {a[5:0],2'b0}://010
// (b[2:0] == 3) ? {a[4:0],3'b0}://011
// (b[2:0] == 4) ? {a[3:0],4'b0}://100
// (b[2:0] == 5) ? {a[2:0],5'b0}://101
// (b[2:0] == 6) ? {a[1:0],6'b0}://110
// (b[2:0] == 7) ? {a[0],7'b0}://111
// 8'hzz;

assign s1 = b[0]? {a[6:0],1'b0}: a;
assign s2 = b[1]? {s1[5:0],2'b0}: s1;
assign s = b[2] ? {s2[3:0],4'b0}:s2;

endmodule // shift_left_logic_8

SV SLL testbench:

// test bench for shift left logic
module testbench;

wire [7:0] s;
reg [7:0] a, b;
integer i;
shift_left_logic_8 sll(s, a, b);

initial begin
#0 a = 8'h00;b = 8'h00;
#10;
for (i = 1;i ＜= 7;i = i + 1)
begin
a = a + 8'h04;
b = b + 8'h01;
#10;
end;
a = 8'hF6;
b = 8'h0A;
#10;
end
endmodule

VHDL SLL RTL code:

---- behavioral model shift left logic b is 2 to 0 for sll
library ieee;
entity shift_left_logic_8 is
port ( s: out std_logic_vector(7 downto 0);
a: in std_logic_vector(7 downto 0);
b: in std_logic_vector(7 downto 0));
end shift_left_logic_8;

architecture behav of shift_left_logic_8 is
signal s1, s2: std_logic_vector(7 downto 0);-- shift by 1,2...signals
begin
--s ＜= a sll to_integer(unsigned(b (2 downto 0))); --enable vhdl 2008 for sll
--s ＜= std_logic_vector(shift_left(unsigned(a), --shift left
--to_integer(unsigned(b (2 downto 0)))));--original code

-- s ＜= a when b(2 downto 0) = "000" else
-- a(6 downto 0) & '0' when b(2 downto 0) = "001" else
-- a(5 downto 0) & "00" when b(2 downto 0) = "010" else
-- a(4 downto 0) & "000" when b(2 downto 0) = "011" else
-- a(3 downto 0) & "0000" when b(2 downto 0) = "100" else
-- a(2 downto 0) & "00000" when b(2 downto 0) = "101" else
-- a(1 downto 0) & "000000" when b(2 downto 0) = "110" else
-- a(0) & "0000000" when b(2 downto 0) = "111" else
-- x"ZZ";

s1 ＜= a(6 downto 0) & '0' when b(0) = '1' else a;
s2 ＜= s1(5 downto 0) & "00" when b(1) = '1' else s1;
s ＜= s2(3 downto 0) & "0000" when b(2) = '1' else s2;

end behav;

VHDL RTL testbench:

-- test bench for shift left logic b is sll only for 2:0 bits
library ieee;
entity testbench is
end testbench;

architecture behav of testbench is
component shift_left_logic_8 is
port ( s: out std_logic_vector(7 downto 0);
a: in std_logic_vector(7 downto 0);
b: in std_logic_vector(7 downto 0));
end component;

signal s,a,b: std_logic_vector( 7 downto 0);
begin
sll8: shift_left_logic_8 port map(s, a, b);

process begin
a ＜= x"00";b ＜= x"00";
wait for 10 ns;
for j in 1 to 7 loop
a ＜= a + x"04";
b ＜= b + x"01";
wait for 10 ns;
end loop;
A ＜= x"F6";
B ＜= x"0A";
wait for 10 ns;
wait;

end process;
end behav;