Function syntax in Verilog(4:1 mux implementation using 2:1 mux)

Functions are sections of Verilog code that allow the Digital Designer to write more reusable and maintainable code. Often a function is created when the same operation is done over and over throughout Verilog code. Rather than rewriting code, one can just call the function. This prevents copy and paste errors and allows for more maintainable code: if the behavior of the function changes, it only needs to be updated in one location.