Все публикации

0:05:06

Hypothesis Testing

0:07:49

Control Hazard - Pipeline || CO

0:02:58

How to Remember Write Through and write Back Cache Updation Policies || OS

0:04:47

Modes of Data transfer Interrupt I/O || CO

0:04:30

Modes of Data Transfer - Programmed I/O with Analogy || CO

0:04:28

Modes of DMA transfer : Burst Mode, Cycle stealing mode & Interleaving Mode || CO

0:05:18

DMA : Direct Memory Access with Analogy || CO

0:10:00

Equivalences involving Quantifiers || DM

0:06:07

Example of DFS Traversal using Adjacency List - Odia || DS

0:03:03

Concept of Virtual Memory || OS

0:02:24

Insertion to AVL tree - Introduction || DS

0:02:01

Broadcasting, Unicasting, Multicasting || CN

0:05:40

Insertion in AVL tree - LR imbalance || DS

0:03:19

Insertion in AVL tree - RL imbalance and examples at the End of the Video|| DS

0:05:19

Deletion in AVL tree - Imbalances and solutions || DS

0:03:06

Insertion in AVL tree : LL Imbalance - DS

0:02:29

Deletion in AVL tree - Introduction || DS

0:02:21

Insertion in AVL tree - RR imbalance

0:05:15

Boruvka's Algorithm - Odia

0:07:02

Prim's Algorithm - Odia

0:07:42

Master's Theorem (Subtraction and Division) to find Time complexity

0:06:44

AVL Tree / BST - Binary Search Tree

0:07:13

MultiStage Graph | DAA - ODIA

0:10:32

ROW AND COLUMN MAJOR ORDER OF ARRAY