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0:00:16

June 19, 2025

0:17:13

Intro to Networking - myHDL (Part1)

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Enjoying Northern Cardinal in backyard

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WaveDrom Bitfield Diagrams for Specifications

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FPGA/ASIC - Draw waveforms for your design

0:28:45

MYHDL - Single Clock FIFO Design

0:21:46

Intro to FPGA Design in Python based MYHDL

0:07:15

Star Trek Time Travel Paradox - Part II

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Star Trek Time Travel Paradox - Part I

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Star Trek Subspace Communication

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Star Trek Transporter - In One Minute

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Space Race - Part II (Return of NASA)

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Star Trek Technology - Drives and Torpedoes

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Sci Fi and Dystopian AI

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How to Design DRAM Controller

0:18:23

DPDK - Simple forwarding app

0:15:44

Buildroot - QEMU-x86-64 tinkering with packages

0:13:53

CRC Parallel Computation, High Speed CRC

0:07:23

RESET Design in Digital Systems

0:11:34

PTP Accuracy - Asymmetry in Networks

0:07:27

AI/ML Emerging FP8 specification and Chips

0:15:07

Lockless Queues

0:08:40

HBM Memory Advances

0:12:11

Fixed Point Math - Part 3