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AAS ASCII Adjust after Subtraction arithmetic instruction in 8086

Implementation of 32:1multiplexer using 4:1 multiplexer

Implementation of full adder using decoder

Implementation of full adder using 8:1 multiplexer

Implementation of 16:1 multiplexer using 4:1 multiplexer

3:8 decoder 74138

8:1 multiplexer

21.14 IMUL signed multiplication arithmetic instruction in 8086

21.13 MUL multiplication arithmetic instruction in 8086

21.10 CMP compare arithmetic instruction in 8086

21.9 NEG negation arithmetic instruction in 8086

21.8 DEC decrement arithmetic instruction in 8086

21.5 DAA Decimal adjust after Addition arithmetic instruction in 8086

21.7 SBB arithmetic instruction in 8086

21.6 SUB arithmetic instruction in 8086

20.8 LEA effective address transfer instruction in 8086

20.10 LES load extra segment register-address transfer instruction

20.11 LAHF load flag register to AH register - data transfer instruction in 8086

21.1 ADD addition performing arithmetic instruction in 8086

20.13 PUSHF and POPF flag transfer instruction in 8086

20.5 XLATB data transfer instruction in 8086

20.12 SAHF store AH to Flag register data transfer instruction

20.7 OUT output port data transfer instruction

20.6 IN input port data transfer instruction in 8086