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0:00:43

50 Years of Moore's Law

0:00:38

Super Bowl LVII Winner Odds

0:00:20

Daily Tata Steel Chess Winner Odds (2023)

0:00:25

Rise of Women in US/Global Politics

0:00:23

US Government Spending by Category

0:00:58

Rise of Democracy by Continent

0:00:57

Deaths by Natural Disaster

0:00:38

US Crime/Prison Population

0:00:26

FIFA World Cup Winner Odds (2022)

0:01:26

What's an FPGA?

0:02:01

UBC Capstone: The ATLUS (Sponsored by DarkVision)

0:04:06

Is Automation Ethical?

0:04:58

How to Write a SystemVerilog TestBench (SystemVerilog Tutorial #3)

0:07:36

How to Simulate and Test SystemVerilog with ModelSim (SystemVerilog Tutorial #2)

0:05:38

How to Write an FSM in SystemVerilog (SystemVerilog Tutorial #1)

0:01:39

How to Convert Between Binary/Hex/Decimal Bases with the HP-50g

0:02:54

How to Generate References with LaTeX (BibTeX)

0:02:23

How to Convert Units with the HP-50g

0:01:18

How to do Logarithms of Different Bases with the HP-50g

0:04:10

Intro to Cadence 2: Creating a Simulation and Testbench

0:04:34

Intro to Cadence 1: Creating a Schematic and Symbol

0:03:55

Introducing the Flat-50G (a non-ugly HP-50g emulator skin)

0:03:53

Introduction to Phasors, Impedance, and AC Circuits

0:01:22

How to Debug VBScript (Visual Studio)