Setting Analysis Options and Timing Budget for Power-Aware Parallel Bus: Part 4

For an accurate analysis of DDR4, it is very important to incorporate the Power Delivery Network into the simulation and analyze the effect of noise due to switching of the parallel bus signal groups.

Part 4 of 5 in this video series will teach you how to:
Setup timing budget parameters
Configure Simulation Analysis options
Configure On die package parasitics for the controller and Memory

[00:00] Introduction
[00:17] Loading the Project
[00:36] Setting a Timing Budget
[01:44] Setting Analysis Options
[05:51] Editing Properties for Transmitter and Receiver Blocks
[06:35] Saving the Topology

Do you have any questions, tips, or ideas about DDR Simulation and Analysis? Let us know in the comments section below!
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