In Hindi | Timing and Control in 8085 | Control Segment - Status Signals, DMA Signals, RESET signals

Hi everyone,
This is my video on explanation of the signals that are the part of Control Segment. They are divided into 4 groups- Control signals, Status Signals, DMA Signals and RESET signals. I have explained with the help of diagrams and tables about how these behave.
I hope you will understand everything I have tried to explain. If you understood the things then requesting you to please like this video and Subscribe to this channel since it matters a lot to me.
YEEEEEEEEESSSSSSSSSSS::::::::::::One thing more AT 14:17 in this video I told you that in the comment I will update about the values of RD bar and WR bar so I am putting the same update here as well : So here it is :
FOR MEMORY FETCH
IO/M bar : 0 || S0=1 || S1=1 || RD bar = 0 || WR bar = 1 (REASON: During Opcode fetch the Opcode is read from the memory location i.e. the HEX CODE of 1 byte is read by the microprocessor from the specific Memory address and i.e. why RD bar will be in active state i.e. RD bar=0)
Thank you!

Stay tuned for the upcoming videos:)

[_eezi]

AT 14:17 in this video I told you that in the comment I will update about the values of RD bar and WR bar for Memory Fetch operation so I am putting the update here: So here it is :
FOR MEMORY FETCH
IO/M bar : 0 || S0=1 || S1=1 || RD bar = 0 || WR bar = 1
[REASON: During OPCODE FETCH the Opcode is read from the memory location i.e. the HEX CODE of 1 byte is read by the microprocessor from the specific Memory address and i.e. why RD bar will be in active state i.e. RD bar=0]