CombCkt - 21 - Gate Sizing for Large Circuits

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CombCkt - 21 - Gate Sizing for Large Circuits
  1. NPTEL-NOC IITM
  2. CombCkt - 21 - Gate Sizing for Large Circuits
  3. NPTEL
  4. SWAYAM
  5. Prof Janakiraman
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He is the best teacher.

I literally spend 40-50 minutes watching his 25 min lecture.

Initially I wasn't understanding Why he is not using Path delay Optimisation.
BUT as I moved on in lecture, he throughly explains it...
🎉

pawansharma
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Anyone, please answer.
Why that particular path is taken when sizing was not done?? 12:51
In the last example, sizing was available, so we got the critical path to be that one.

Abhish_
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26:36 How to solve for x1, x2, using the given constraints?

AbhishekSingh-uprv
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14:30
Increasing capacitance by factor of stage effort how ?

nityanand